In this section we look at some other popular processors: the MSP430 (another RISC-but-in-many-ways-not MCU); the venerable 8051 and the current king of MCUs, the ARM (Cortex M0).
The MSP430 is like a stripped-down pdp-11 with 16x16-bit registers and single-cycle instructions. But it's not great for computing 16-bit CRCs. This routine weighs in at 58 bytes and 28 cycles per byte, making it the same length and relatively the same performance as an H8. Only the 6502 is longer! The Msp430 has some features going for it, like it's ability to swap bytes and shift whole words in a single cycle, but the reason it's not as fast as a PIC or AVR is primarily because the MSP430 has no nybble operations and because sometimes its byte operations (which modify the whole word of the destination register, by zero-extending the result) get in the way. The MSP430's straight-forward <<5 is faster than the rotate right 3 times technique used on some 8-bit CPUs, because it doesn't need to save an intermediate and apply mask operations. But the neatest trick here is the >>4 . By zero-extending r4.b when moving into r7, we clear the upper byte, so '0' bits get shifted into bits 4..7 of r7. Then by zero-extending r7 again, we clear r7's original bits 3..0; and so we get a byte shift, in 1 cycle less than applying a mask.
Crc16Msp430:
push r7
Crc16Msp430Loop:
swpb r5 ;crc=(crc>>8)(crc<<8)
mov.b @r4+,r7 ;r7=new byte.
xor r7,r5 ;r5=crc^=newByte.
mov.b r5,r7 ;r7=crc and 255;
rra r7
rra r7
rra r7
rra r7
mov.b r7,r7 ; clears bits 7 to 15 giving the >>4
xor r7,r5
mov.b r5,r7 ;Sign extend again.
swpb r7 ;<<8
add r7,r7
add r7,r7
add r7,r7
add r7,r7 ;<<12
xor r7,r5
mov r5,r7 ;crc and 255 again.
add r7,r7
add r7,r7
add r7,r7
add r7,r7
add r7,r7 ;<<5
xor r7,r5
Dec r6
jne Crc16Msp430Loop
pop r7
ret ;
Crc16_8051:
push r3
Crc16_8051Loop:
movx acc,@dptr
inc dptr
xrl a,r1
mov r3,a
swap
anl a,15;
xrl a,r3
mov r3,a
swap
anl a,240 ;<<12
xrl a,r0
mov r1,a
mov a,r3
swap
rl a ;<<5
mov r0,a ;save
anl a,31
xrl a, r1
mov r1,a
mov a,r1
anl a,240
xrl a,r3
mov r0,a
djnz r2,Crc16_8051Loop
pop r3
ret
c65535: .word 65536
Crc16_Thumb:
push {r3,r4}
ldr r4,[PC,c65535]
Crc16_ThumbLoop:
lsl r3,r0,#8
lsr r0,r0,#8
orr r0,r3
and r0,r4
ldrb r3,[r1],#1
eor r0,r3
mov r3,#240
and r3,r0
lsr r3,r3,#4
eor r0,r3
lsl r3,r0,#12
eor r0,r3
lsl r3,r0,#5;
eor r0,r3
and r0,r4
subs r2,#1
bne Crc16_ThumbLoop
pop {r3,r4}
rts
;z^Data, r25:r24=Crc16, r26=Len.
Crc16Lo=r24
Crc16Hi=r25
BuffLo=r26,
BuffHi=r27
temp=r26
Len=r28
Crc16_AtMega:
push r16
push r30
push r31 ;used to hold buff.
movw z,BuffLo
ldi r16,16
ldi r27,32
Crc16_AtMegaLoop:
mov temp,Crc16Lo
mov Crc16Lo,Crc16Hi
mov Crc16Hi, temp ; Swap hi and lo.
ld temp,Z+
eor Crc16Lo, temp ; crc^=ser_data;
mul r16,Crc16Lo ; Faster than executing lsr 4 times.
eor Crc16Lo, r1 ; crc^=(crc&0xff)>>4
mul r16,Crc16Lo ;(crc&0xff)<<4
eor Crc16Hi,r0 ;crc^=(crc<<8)<<4
;(r0 wonderfully contains the other 4 bits)
mul r27,Crc16Lo ; (crc&0xff)<<5
eor Crc16Lo,r0
eor Crc16Hi,r1
subi Len,1
bne Crc16_AtMegaLoop
pop r31
pop r30
pop r16
ret
In the above version (designed for a Mega AVR), we can save a cycle from the mov, swap, andi sequence by making use of the mul instruction. We can save 5 cycles in the <<5 code. This gives us 19cycles per byte, just 1 cycle longer than an ARM thumb (and the same length). Yet it's 7 cycles shorter than the other AVR version (53% faster!).
