Accessing Ram on an Intel 4004

Hi folks,

I've recently been trying to work out how RAM is accessed on an Intel 4004, 4-bit Microprocessor. The most valuable information I've found is from:

http://e4004.szyc.org/iset.html

Whose website provides a javascript emulator for the 4004.



The 4004 is a seriously primitive device. One of its odd behaviours is that it doesn't really address RAM as such. What it does is provide a means of sending an address to a RAM chip and it expects each RAM chip to contain its own address register, this is done with an SRC ixr instruction, which outputs the contents of one of its 8 * 4-bit register pairs on its multiplexed address bus, selecting RAM if the upper 2 bits are [This bit I don't know] and ROM if the upper 2 bits are [Similarly Unknown].

Ram is organised as follows:

You can have up to 8 RAM bank chips which are selected using DCL nnn instructions which simply output nnn to CM lines 1..3 on the chip. (There's the default Ram Bank 0 which is selected when nnn=0, which activates CM0, and the rest nnn>0 which literally output to CM1..CM3, so you can attach a 3:8 decoder and decode the other 8 - though that doesn't quite make sense).

Next up: The Src instruction outputs a register pair as described above. The top 2 bits are ignored by the RAM chip itself. The bottom 6 bits select one of 64 addresses (4 registers of 16 4-bit 'characters'). You can then transfer between RAM and the Accumulator using RDM (to read from the RAM address), WRM ( to write Acc to the RAM). There's also ADM and SBM to add (with carry) and subtract (with borrow) the addressed RAM nybble to/from the Acc (and store in the Acc).

In addition, each 4004 RAM chip supports 4 'status characters', per register - bonus nybbles, so each register really contains 20 nybbles. You can access these using RD0 to RD3 and WR0 to WR3, so you can't index them via registers. It's all very strange.

But it gets stranger still. I/O is also accessed via the RAM and ROM chips which each provide 4-bits of I/O (RAM is output only) which you can access via RDR (read ROM port), WRR (write ROM port), and WMP (to write to the RAM output port).

Anyway, this blog explains why you can access 5120 bits of RAM: (8 RAM banks selected via DCL * 4 registers * 20 nybbles/register) * 4-bits / nybble = 5120 bits.